DDR protocol refers to a data transfer protocol that allows for data to be fetched on both the rising and falling edges of a clock (referred to as a data strobe or DQS), thus doubling the effective data transfer rate.
FIG. 1 shows a system 100 for DDR data transfer. A first data processing device 110 includes a DQS driver 112 and a data driver 114 for driving (respectively) a clock signal and data to another device such as device 120 via a DQS bus 130 and a data bus 140. Device 110 also includes a DQS receiver 113 to receive a clock signal via DQS bus 130 and a data receiver 115 to receive data via data bus 140. System 100 uses parallel termination for DQS bus 130; that is, bus 130 is in communication with a termination voltage Vtt via a resistor 150 with resistance R.
According to DDR protocol, a device driving data also drives the DQS signal. That is, if device 110 is driving data to device 120 via data bus 140, device 110 is also driving a DQS signal to device 120 via DQS bus 130. Conversely, if device 120 is driving data to device 110, it is driving both the data and the DQS signal.
FIG. 2 shows an example of a signal on a parallel terminated DQS bus 130 as a function of time, as first device 110 sends data to second device 120, which in turn sends data to first device 110.
Prior to transmitting data, first device 110 pulls the voltage on DQS bus 130 to zero, then transmits the clock signal as shown. First device 110 concludes data transmission at t1 by transmitting a zero on DQS bus 130. First device 110 then relinquishes control of DQS bus 130.
Between t1 and t2, neither device is transmitting data, so neither is driving a signal on DQS bus 130. For a series terminated bus, the voltage on DQS bus 130 would generally remain in the most recently asserted (zero) state. However, for a parallel terminated bus (as shown in FIG. 1), the voltage on DQS bus 130 drifts up to the termination voltage Vtt. Vtt is generally a voltage that corresponds to neither a logical one nor a logical zero. Therefore, for parallel termination, DQS bus 130 is generally in an unknown state between the time first device 110 relinquishes bus 130 (t1) and the time the second device 120 drives bus 130 to the zero state (t2). When bus 130 is in an unknown state, associated input devices, such as devices 110 and 120, are unable to discern a change in state corresponding to a device taking control of bus 130. Devices 110 and 120 may thus be unable to determine whether DQS bus 130 and data bus 140 are available to transmit data to another device.